Note: This is the 2011鈥�2012 edition of the eCalendar. Update the year in your browser's URL bar for the most recent version of this page, or click聽here to jump to the newest eCalendar.
Overview
Electrical Engineering : Trends in technology. CISC vs. RISC architectures. Pipelining. Instruction level parallelism. Data and Control Hazards. Static prediction. Exceptions. Dependencies. Loop level paralleism. Dynamic scheduling, branch prediction. Branch target buffers. Superscalar and N-issue machines. VLIW. ILP techniques. Cache analysis and design. Interleaved and virtual memory. TLB translations and caches.
Terms: Fall 2011, Winter 2012
Instructors: Meyer, Brett (Fall) Mihajlovic, Bojan (Winter)